The pitch of metal wiring lines and the pitch of gates in chips have been decreasing in order to improve the gate density in the chips. Due to this, the parasitic capacitance of wires has become an important factor, besides the performance of transistors, in designing circuit layouts for improving the performance of CMOS circuits.
Element structures taking into account the parasitic capacitance around transistors have been proposed. It is known with respect to such element structures that when the pitch of gates of transistors is reduced to improve the degree of integration, the height of the gates and the height of plugs connecting to the transistors are important factors to reduce the parasitic capacitance around the gates of the transistors. This means that, in order to reduce the gate capacitance, the gate should be designed to have a low height. In conventional designs, however, wiring line layouts have not been considered. In other words, the wiring line parasitic capacitance caused in three-dimensional designs of transistors has not been considered.
A circuit layout is known, in which a circuit is divided into circuit blocks, and folded in units of the circuit blocks. This layout is intended to reduce the wiring line length, but does not take the capacitive coupling into consideration.